Hi3559av100使用8路mipi输入失败
使用环境是6路TC3587,是一个并口转mipi的套片,可以近似理解为一个传感器,接了hi3559av100的0-5路mipi输入,hi3559av100使用的是模式11。六个TC3587同时配置,并且同步他们的输入行场信息,他们出来的mipi信号行场信息是否同步未知。
现在的结果是:将hi3559配置成x2x2x2x2x2x2x2x2时,只有DEV1,3,5有视频输出,DEV0,2,4没有视频输出。
proc/umap/hi_mipi显示的信息时DEV0,2,4检测不到同步信号。
将将hi3559配置成X4X4X4模式时,DEV0,2,4有视频输出。
6路TC3587的配置在上述的两种测试条件中保持不变,可以认为MIPI设备的输入信息没有错误。
联系了海思技术支持,说时同一个phy上面的行场信息要保持同步。
请问如果一个phy上同时接入了两个mipi设备,怎么保证两个设备的行场信息同步,是否可以这样接?需要什么特殊的条件?还有行场信息保持同步的含义时使用相同的行场信息,还是行场信息的包要同时传输到3559?
Module: [MIPI], Build Time: [Dec 21 2018, 17:12:09]
-----MIPI LANE DIVIDE MODE---------------------------------------------------------------------------------------------
MODE LANE DIVIDE
11 2+2+2+2+2+2+2+2
-----MIPI DEV ATTR-----------------------------------------------------------------------------------------------------
Devno WorkMode DataRate DataType WDRMode linkId ImgX ImgY ImgW ImgH
0 MIPI X1 YUV422 None 0 0 0 1920 1080
1 MIPI X1 YUV422 None 1 0 0 1920 1080
2 MIPI X1 YUV422 None 2 0 0 1920 1080
3 MIPI X1 YUV422 None 3 0 0 1920 1080
4 MIPI X1 YUV422 None 4 0 0 1920 1080
5 MIPI X1 YUV422 None 5 0 0 1920 1080
-----MIPI LANE INFO-----------------------------------------------------------------------------------------------------
Devno LaneCnt LaneID
0 2 0, 2, -1, -1, -1, -1, -1, -1
1 2 1, 3, -1, -1, -1, -1, -1, -1
2 2 4, 6, -1, -1, -1, -1, -1, -1
3 2 5, 7, -1, -1, -1, -1, -1, -1
4 2 8, 10, -1, -1, -1, -1, -1, -1
5 2 9, 11, -1, -1, -1, -1, -1, -1
-----MIPI link INFO------------------------------------------------------
linkIdx LaneCount LaneId PhyData0 PhyData1 AlignedData0 AlignedData1 ValidLane
0 2 0, 2 0xff 0xff 0xff 0xff 0, 2
1 2 1, 3 0xff 0xff 0xff 0xff 1, 3
2 2 4, 6 0xff 0xff 0xff 0xff 4, 6
3 2 5, 7 0x0 0x0 0x3a 0x1d 5, 7
4 2 8,10 0xff 0xff 0xff 0xff 8, 10
5 2 9,11 0xff 0xff 0xff 0xff 9, 11
-----MIPI DETECT INFO----------------------------------------------------
Devno VC width height
0 0 0 0
0 1 0 0
0 2 0 0
0 3 0 0
1 0 1920 1080
1 1 0 0
1 2 0 0
1 3 0 0
2 0 0 0
2 1 0 0
2 2 0 0
2 3 0 0
3 0 1920 1080
3 1 0 0
3 2 0 0
3 3 0 0
4 0 0 0
4 1 0 0
4 2 0 0
4 3 0 0
5 0 1920 1080
5 1 0 0
5 2 0 0
5 3 0 0
-----FSM TIMEOUT AND ESCAPE INFO---------------------------------------------
phy clkTOutCnt d0TOutCnt d1TOutCnt d2TOutCnt d3TOutCnt clkEscCnt d0EscCnt d1EscCnt d2EscCnt d3EscCnt
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0 0
-----MIPI INT ERROR INFO-----------------------------------------------------------
Devno vc0CRC vc1CRC vc2CRC vc3CRC vc0OrderErr vc1OrderErr vc2OrderErr vc3OrderErr vc0NMatCnt vc1NMatCnt vc2NMatCnt vc3NMatCnt
0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0 0 0 0
Devno HCntErr vc0HECC vc1HECC vc2HECC vc3HECC vc0DtErr vc1DtErr vc2DtErr vc3DtErr
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
Devno CMD_FIFO_RERR DATA_FIFO_RERR CMD_FIFO_WERR DATA_FIFO_WERR
0 0 0 0 0
1 0 0 0 0
2 0 0 0 0
3 0 0 0 0
4 0 0 0 0
5 0 0 0 0
-----ALING ERROR INFO--------------------------------------
Devno FIFO_FullErr Lane0Err Lane1Err Lane2Err Lane3Err Lane4Err Lane5Err Lane6Err Lane7Err Lane8Err Lane9Err Lane10Err Lane11Err Lane12Err Lane13Err Lane14Err Lane15Err
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Devno FIFO_FullErr Lane0Err Lane1Err Lane2Err Lane3Err Lane4Err Lane5Err Lane6Err Lane7Err Lane8Err Lane9Err Lane10Err Lane11Err Lane12Err Lane13Err Lane14Err Lane15Err
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Devno FIFO_FullErr Lane0Err Lane1Err Lane2Err Lane3Err Lane4Err Lane5Err Lane6Err Lane7Err Lane8Err Lane9Err Lane10Err Lane11Err Lane12Err Lane13Err Lane14Err Lane15Err
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Devno FIFO_FullErr Lane0Err Lane1Err Lane2Err Lane3Err Lane4Err Lane5Err Lane6Err Lane7Err Lane8Err Lane9Err Lane10Err Lane11Err Lane12Err Lane13Err Lane14Err Lane15Err
3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Devno FIFO_FullErr Lane0Err Lane1Err Lane2Err Lane3Err Lane4Err Lane5Err Lane6Err Lane7Err Lane8Err Lane9Err Lane10Err Lane11Err Lane12Err Lane13Err Lane14Err Lane15Err
4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Devno FIFO_FullErr Lane0Err Lane1Err Lane2Err Lane3Err Lane4Err Lane5Err Lane6Err Lane7Err Lane8Err Lane9Err Lane10Err Lane11Err Lane12Err Lane13Err Lane14Err Lane15Err
5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0